computer-architecture

computer-architecture

PowerPC disassembler output different from opcodes

Floating Point Number to Null-Terminated ASCII String

Static Hazard 1 and One Circuit Problems?

MIPS R4000 Latency and Initiation Intervals

Different schemes of two-bit branch prediction

2-way set associative cache hit/miss checking

How to know the statistic of the instructions begin run

Datapath for a jump instruction(MIPS)

How does CPU access BIOS instructions stored in external memory?

Converting SRAM to another SRAM

what is difference between instruction access and data access

what is “sw $fp($sp)” mean in MIPS

Use of learning computer system architecture? [closed]

how does so how does the computer interpret the result of unsigned/signed arithmetic if it is to be used again

What is a shadowed register file and what is a narrow register file?

Making a pipelined processor with instructions issued in alternate clock cycles

SoC and computer architecture

Will RISC architecture processors outperform that of CISC in future

What is the speedup? Can't understand the solution

For a Single Cycle CPU How Much Energy Required For Execution Of ADD Command

the name of state when data reading from hard drive

Hazard Type - Computer Architecture

C to NIOS II program

Digital Design simple operation finding of Mux and Decode?

Encoder and My Challenges on Digital Logic

For a 2GBytes memory, suppose its memory width is 8 bits: what is the address space of the memory?

Number of Prime Implicant and EPI

Load immediate direct

Flynn's Bottleneck - maximum speedup 2

How to use Simplescalar, sim-outorder simulator to correctly model “my” systems specs (intel i7) with configuration files?

The characters entered through keyboard gets converted to equivalent ASCII code & stored on RAM in the binary form.How it happens

Defining locality in pseudocode

I'm struggling with writing the truth table for this state diagram for jk flip flops

Integer instructions can go past branches.what does this mean?

Memory capacity of a RAM [closed]

How/does DMA handle multiple concurrent transfers?

What is the Reservation Table for the following pipeline?

Parallel lookup in L1 / L2 / LLC / DRAM?

What are the performance and architectural differences between PCIe and QPI?

gem5 cache statistics - reset and dump

minimum number of bits in a microinstruction to specify two kinds of microoperations?

How do i calculate the size of a tag field?

Computer architecture : how to encode an instruction?

In asynchronous serial transmission start bit is o or 1?

Calculate the performance of a multicore architecture?

How do I simplify minterms of a truth table?

Is precise interrupt important from software's point of view?

How many bits do i need to store AB+C?

Calculate the time for executin instructions with pipeline

How can we reduce page fault

Can interpreted languages use delay slots?

Why speedup reduces with increase in number of pipeline stages?

What is an Instruction Set Architecture (ISA)

what is the difference between DX,SX,LX [closed]

Interrupt time in DMA operation

Digital Computer Architecture Help Needed [closed]

CPU(central processing unit) & Microprocessor

Understanding stalls and branch delay slots

All real numbers that have more than 1 representation in IEEE-754 of single precision

Ghz to MIPS? Rough estimate anyone?

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